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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14023B (see Page 6-5) MC14023UB (see Page 6-14)
MC14024B 7-Stage Ripple Counter
The MC14024B is a 7-stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered. * * * * Diode Protection on All Inputs Output Transitions Occur on the Falling Edge of the Clock Pulse Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Pin-for-Pin Replacement for CD4024B MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 632
P SUFFIX PLASTIC CASE 646
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I
Value Unit V V - 0.5 to + 18.0 Vin, Vout lin, lout PD Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 10 500 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg TL - 65 to + 150 260
D SUFFIX SOIC CASE 751A
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
_C _C
PIN ASSIGNMENT
CLOCK RESET Q7 Q6 Q5 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD NC Q1 Q2 NC Q3 NC
Lead Temperature (8-Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
1 CLOCK C Q C Q C Q C Q
Q4 VSS
VDD = PIN 14 VSS = PIN 7 NC = NO CONNECTION R 2 RESET Q R Q R Q R Q
12 Q1
11 Q2 Q3 = PIN 9 Q4 = PIN 6 Q5 = PIN 5
4 Q6
3 Q7
REV 3 1/94
(c)MC14024B 1995 Motorola, Inc. 100
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III IIII I III IIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIII IIIIII IIII I I I II II II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
MOTOROLA CMOS LOGIC DATA
Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Characteristic "1" Level "0" Level Source Sink Symbol VOH VOL IOH IDD VIH IOL Cin VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 IT = (0.31 A/kHz) f + IDD IT = (0.60 A/kHz) f + IDD IT = (1.89 A/kHz) f + IDD Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 0.00001 - 4.2 - 0.88 - 2.25 - 8.8 Typ # 0.005 0.010 0.015 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
1.0
0.05 0.05 0.05
Max
150 300 600
1.5 3.0 4.0
--
-- -- --
-- -- -- --
-- -- --
-- -- --
MC14024B 101
mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Input Pulse Frequency
Clock Input Rise and Fall Time
Reset Removal Time
Reset Pulse Width
Clock Pulse Width
Propagation Delay Time Clock to Q1 tPLH, tPHL = (1.7 ns/pF) CL + 295 ns tPLH, tPHL = (0.66 ns/pF) CL + 117 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns Clock to Q7 tPLH, tPHL = (1.7 ns/pF) CL + 915 ns tPLH, tPHL = (0.66 ns/pF) CL + 367 ns tPLH, tPHL = (0.5 ns/pF) CL + 275 ns Reset to Qn tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 217 ns tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
MC14024B 102
Characteristic Clock 1 1 0 0
TRUTH TABLE
Reset
tTLH, tTHL
1
0
1
0
1
0
1
0
Symbol
tPLH, tPHL
tTLH, tTHL
trem
tWH
tWH
fcl
Advance One Count
All Outputs Low
All Outputs Low
All Outputs Low
All Outputs Low
No Change
No Change
No Change
VDD
State
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
Min
625 190 145
600 350 260
500 165 125
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
MOTOROLA CMOS LOGIC DATA
Typ # 1000 400 300 250 75 50 375 200 150 200 60 40 500 250 180 380 150 110 100 50 40 2.5 8.0 12 -- -- -- 2000 750 565 Max 800 400 300 600 230 175 200 100 80 1.0 8.0 200 -- -- -- -- -- -- -- -- -- 1.0 3.0 4.0 MHz Unit s ms s ns ns ns ns ns
VDD VDD
VOL = Vout
VDD
VOH = Vout
C Qn R VSS IOH EXTERNAL POWER SUPPLY
C Qn R VSS IOL EXTERNAL POWER SUPPLY
COUNT Qn TO A LOGIC "1" LEVEL.
Figure 1. Typical Output Source Characteristics Test Circuit
Figure 2. Typical Output Sink Characteristics Test Circuit
VDD 500 F ID 0.01 F CERAMIC
PULSE GENERATOR
f
C Q1 Q2 Q3 Q4 Q5 Q6 R Q7 CL VSS
CL CL CL CL CL CL
Figure 3. Power Dissipation Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14024B 103
MC14024B 104
t WL t WH 1 t rem 50% t PLH1 t PHL1 90% 50% t PHL2 90% 50% 10% t TLH t PLH3 50% t PHL3 t THL t R3 t THL t R2 10% t TLH t PLH2 t R1 50% 2 4 8 16 32 64 128 255 t TLH t PLH4 t PHL4 50% t TLH t PLH5 t PHL5 50% t TLH t PHL6 t PLH6 50% t TLH t PLH7 t PHL7 t THL 90% 10% t THL t R7 t R6 t THL t R5 t THL t R4 t TLH t THL Input t TLH and t THL = 20 ns
VDD VSS VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL
CLOCK (1)
RESET (2)
Q1 (12)
Q2 (11)
Q3 (9)
Figure 4. Functional Waveforms
Q4 (6)
Q5 (5)
Q6 (4)
MOTOROLA CMOS LOGIC DATA
Q7 (3)
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01
-A-
14 9
-B-
1 7
C
L
-T-
SEATING PLANE
K F D
14 PL
G 0.25 (0.010)
M
N J TA
S 14 PL
M 0.25 (0.010)
M
TB
S
DIM A B C D F G J K L M N
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
MOTOROLA CMOS LOGIC DATA
MC14024B 105
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC14024B 106
*MC14024B/D*
MOTOROLA CMOS LOGIC DATA MC14024B/D

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